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19-4099; Rev 0; 4/08
1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
General Description
The MAX16060/MAX16061/MAX16062 are 1% accurate, quad-/hex-/octal-voltage P supervisors in a small thin QFN package. These devices provide supervisory functions for complex multivoltage systems. The MAX16060 monitors four voltages, the MAX16061 monitors six voltages, and the MAX16062 monitors eight voltages. These devices offer independent outputs for each monitored voltage along with a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds (down to 0.4V) or the manual reset input is asserted. The reset output remains asserted for the reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. The minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. All open-drain outputs have internal 30A pullups that eliminate the need for external pullup resistors. However, each output can be driven with an external voltage up to 5.5V. Other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. An additional feature is a watchdog timer that asserts RESET when the watchdog timeout period (1.6s typ) is exceeded. The watchdog timer can be disabled by leaving WDI unconnected. These devices are offered in 16-, 20-, and 24-pin thin QFN packages (4mm x 4mm) and are fully specified from -40C to +125C.
Features
o Fixed Thresholds for 3.3V, 2.5V, and 1.8V Systems o Adjustable Thresholds Monitor Low Voltages (Down to 0.4V) o 1% Accurate over Temperature o Open-Drain Outputs with Internal Pullups Reduce the Number of External Components o Fixed 140ms (min) or Capacitor-Adjustable Reset Timeout o Manual Reset, Margin Enable, and Tolerance Select Inputs o Watchdog Timer 1.6s (typ) Timeout Period 54s Startup Delay After Reset o Monitors Four (MAX16060), Six (MAX16061), or Eight (MAX16062) Voltages o RESET Output Indicates All Voltages Present o Independent Voltage Monitors o Guaranteed to Remain Asserted Down to VCC = 1V o Small (4mm x 4mm) Thin QFN Package
MAX16060/MAX16061/MAX16062
Applications
Storage Equipment Servers Networking/Telecommunication Equipment Multivoltage ASICs Automotive
Typical Operating Circuit
Ordering Information
PART MAX16060_TE+ MAX16061_TP+ MAX16062_TG+ TEMP RANGE -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 16 TQFN-EP* 20 TQFN-EP* 24 TQFN-EP*
VIN1 VIN2 VIN3
VCC IN1 IN2 IN3
SRT
MARGIN RESET WDI RST P I/O
MAX16061A
VIN4 VIN5
IN4 IN5
OUT1 OUT2 OUT3
Note: The "_" is a placeholder for the input voltage threshold. See Table 1. The MAX16060/MAX16061/MAX16062 are available in factory-preset thresholds/configuration combinations. Choose the desired combination and complete part number from Table 1. +Denotes a lead-free package. For tape-and-reel, add a "T" after the "+." Tape-and-reel are offered in 2.5k increments. *EP = Exposed pad.
VIN6
IN6
OUT4 OUT5 OUT6
MR
GND
TOL
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
ABSOLUTE MAXIMUM RATINGS
VCC, OUT_, IN_, RESET to GND ..............................-0.3V to +6V TOL, MARGIN, MR, SRT, WDI to GND ...........-0.3V to VCC + 0.3 Input/Output Current (RESET, MARGIN, SRT, MR, TOL, OUT_, WDI).........................................20mA Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (derate 16.9mW/C above +70C) ......1349mW 20-Pin TQFN (derate 16.9mW/C above +70C) ......1355mW 24-Pin TQFN (derate 16.9mW/C above +70C) ......1666mW Operating Temperature Range .........................-40C to +125C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C.) (Note 1)
PARAMETER Operating Voltage Range Supply Current (Note 3) UVLO (Undervoltage Lockout) UVLO Hysteresis IN_ (See Table 1) 3.3V threshold, TOL = GND 3.3V threshold, TOL = VCC Threshold Voltages (IN_ Falling) VTH 2.5V threshold, TOL = GND 2.5V threshold, TOL = VCC 1.8V threshold, TOL = GND 1.8V threshold, TOL = VCC Adjustable Threshold (IN_ Falling) IN_ Hysteresis IN_ Input Current VTH VTH_HYS TOL = GND TOL = VCC IN_ rising Fixed thresholds Adjustable thresholds -100 3.069 2.904 2.325 2.200 1.674 1.584 0.390 0.369 3.102 2.937 2.350 2.225 1.692 1.602 0.394 0.373 0.5 3 16 +100 3.135 2.970 2.375 2.250 1.710 1.620 0.398 0.377 V % VTH A nA V SYMBOL VCC ICC VUVLO VUVLO_HYS (Note 2) VCC = 3.3V, OUT_, RESET not asserted VCC = 5V, OUT_, RESET not asserted VCC rising 1.62 CONDITIONS MIN 1.0 45 50 1.80 65 TYP MAX 5.5 65 70 1.98 UNITS V A V mV
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C.) (Note 1)
PARAMETER RESET SRT = VCC Reset Timeout tRP CSRT = 1500pF (Note 4) CSRT = 100pF CSRT = open SRT Ramp Current SRT Threshold SRT Hysteresis IN_ to Reset Delay RESET Output-Voltage Low tRD VOL IN_ falling VCC = 3.3V, ISINK = 10mA, RESET asserted VCC = 2.5V, ISINK = 6mA, RESET asserted VCC = 1.2V, ISINK = 50A, RESET asserted RESET Output-Voltage High MR Input-Voltage Low MR Input-Voltage High MR Minimum Pulse Width MR Glitch Rejection MR to Reset Delay MR Pullup Resistance OUTPUTS (OUT_ ) OUT_ Output-Voltage Low OUT_ Output-Voltage High IN_ to OUT_ Propagation Delay VOL VOH tD VCC = 3.3V, ISINK = 2mA VCC = 2.5V, ISINK = 1.2mA VCC 2.0V, ISOURCE = 6A (VTH + 100mV) to (VTH - 100mV) 0.8 x VCC 20 0.3 0.3 V V s Pulled up to VCC 12 VOH VIL VIH 0.7 x VCC 1 100 200 20 28 VCC 2.0V, ISOURCE = 6A, RESET deasserted 0.8 x VCC 0.3 x VCC ISRT VSRT = 0V 460 1.173 140 2.43 200 3.09 0.206 50 600 1.235 100 20 0.3 0.3 0.3 V V V s ns ns k V 740 1.293 s nA V mV s 280 3.92 ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX16060/MAX16061/MAX16062
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40C to +125C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25C). (Note 1)
PARAMETER WATCHDOG TIMER WDI Input-Voltage Low WDI Input-Voltage High WDI Pulse Width Watchdog Timeout Period Watchdog Startup Period Watchdog Input Current DIGITAL LOGIC TOL Input-Voltage Low TOL Input-Voltage High TOL Input Current MARGIN Input-Voltage Low MARGIN Input-Voltage High MARGIN Pullup Resistance MARGIN Delay Time tMD VIL VIH Pulled up to VCC Rising or falling (Note 6) 0.7 x VCC 12 20 50 28 VIL VIH TOL = VCC 0.7 x VCC 100 0.3 x VCC 0.3 x VCC V V nA V V k s VWDI = 0 to VCC (Note 5) tWDI VIL VIH (Note 5) 0.7 x VCC 50 1.12 35 -1 1.60 54 2.40 72 +1 0.3 x VCC V V ns s s A SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Devices are tested at TA = +25C and guaranteed by design for TA = TMIN to TMAX. Note 2: The outputs are guaranteed to remain asserted down to VCC = 1V. Note 3: Measured with WDI, MARGIN, and MR unconnected. Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worst case of the SRT ramp current and SRT threshold specifications. Note 5: Guaranteed by design and not production tested. Note 6: Amount of time required for logic to lock/unlock outputs from margin testing.
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
NORMALIZED THRESHOLD vs. SUPPLY VOLTAGE
MAX16060/1/2 toc02
MAX16060/MAX16061/MAX16062
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX16060/1/2 toc01
SUPPLY CURRENT vs. TEMPERATURE
60 WDI, MARGIN, AND MR UNCONNECTED 55 SUPPLY CURRENT (A) 50 45 40 VCC = 2.5V 35 30 VCC = 3.3V VCC = 5V 1.0100 1.0075 NORMALIZED THRESHOLD 1.0050 1.0025 1.0000 0.9975 0.9950 0.9925 0.9900 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 1.5 2.0
WDI, MARGIN, AND MR UNCONNECTED 55 SUPPLY CURRENT (A) 50 45 40 35 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0
5.5
2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
NORMALIZED THRESHOLD vs. TEMPERATURE
MAX16060/1/2 toc04
OUTPUT VOLTAGE vs. SINK CURRENT
100
MAX16060/1/2 toc05
OUTPUT VOLTAGE vs. SOURCE CURRENT
MAX16060/1/2 toc06
1.001 1.000 NORMALIZED THRESHOLD 0.999 0.998 0.997
1000
800 VCC - VOUT_ (mV)
75 VOUT_ (mV)
600
50
400
25 0.996 OUT_ LOW 0.995 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0 0 1 2 3 4 5 6 SINK CURRENT (mA) 7 8
200 OUT_ HIGH 0 0 5 10 15 20 SOURCE CURRENT (A) 25 30
MAXIMUM TRANSIENT DURATION vs. INPUT OVERDRIVE
MAXIMUM TRANSIENT DURATION (s) OUTPUT GOES LOW ABOVE THIS LINE
MAX16060/1/2 toc07
RESET TIMEOUT PERIOD vs. TEMPERATURE
197 RESET TIMEOUT PERIOD (ms) 196 195 194 193 192 191 190
MAX16060/1/2 toc08
RESET TIMEOUT DELAY
MAX16060/1/2 toc09
600 500 400 300 200 100 0 1 10 100
198
SRT = VCC -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 40ms/div
1000
INPUT OVERDRIVE (mV)
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MAX16060/1/2 toc03
60
IN1 5V/div
OUT1 2V/div RESET 2V/div
1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
RESET TIMEOUT PERIOD vs. CSRT
MAX16060/1/2 toc10
WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
1.59 WATCHDOG TIMEOUT PERIOD (s) 1.58 1.57 1.56 1.55 1.54 1.53 1.52 1.51
MAX16060/1/2 toc11
1000
1.60
100
tRP (ms)
10
1
0.1 0.01 0.01 0.1 1 10 100 1000 CSRT (nF)
1.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
MARGIN ENABLE FUNCTION
MAX16060/1/2 toc12
MARGIN DISABLE FUNCTION
MAX16060/1/2 toc13
MARGIN 2V/div
MARGIN 2V/div
OUT_ 2V/div
OUT_ 2V/div RESET 2V/div
OUT_ AND RESET ARE BELOW RESPECTIVE THRESHOLDS
OUT_ AND RESET ARE BELOW RESPECTIVE THRESHOLDS 100s/div
RESET 2V/div
100s/div
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
Pin Description (MAX16060)
PIN 1 2 NAME IN3 IN4 FUNCTION Monitored Input Voltage 3. See Table 1 for the input voltage threshold. Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected-state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA. Ground Unmonitored Power-Supply Input Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to V CC . Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
MAX16060/MAX16061/MAX16062
3
WDI
4 5 6 7 8
GND VCC OUT3 OUT4 MR
9
SRT
10 11 12
MARGIN OUT2 OUT1
13
RESET
14 15 16 --
IN1 IN2 TOL EP
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Pin Description (MAX16061)
PIN 1 2 3 NAME IN4 IN5 IN6 FUNCTION Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Monitored Input Voltage 5. See Table 1 for the input voltage threshold. Monitored Input Voltage 6. See Table 1 for the input voltage threshold. Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected-state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA. Ground Unmonitored Power-Supply Input Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Monitored Input Voltage 3. See Table 1 for the input voltage threshold. Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
4
WDI
5 6 7 8 9 10
GND VCC OUT4 OUT5 OUT6 MR
11
SRT
12 13 14 15
MARGIN OUT3 OUT2 OUT1
16 17 18 19 20 --
RESET IN1 IN2 IN3 TOL EP
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
Pin Description (MAX16062)
PIN 1 2 3 4 NAME IN5 IN6 IN7 IN8 FUNCTION Monitored Input Voltage 5. See Table 1 for the input voltage threshold. Monitored Input Voltage 6. See Table 1 for the input voltage threshold. Monitored Input Voltage 7. See Table 1 for the input voltage threshold. Monitored Input Voltage 8. See Table 1 for the input voltage threshold. Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer. The WDI unconnected state detector uses a small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than 200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA. Ground Unmonitored Power-Supply Input Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at IN5 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at IN6 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the voltage at IN7 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the voltage at IN8 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted. MR is pulled up to VCC through a 20k resistor. Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset timeout period can be calculated as follows: Reset Timeout (s) = 2.06 x 106 () x CSRT (F). For the internal timeout period of 140ms (min), connect SRT to VCC. Margin Disable Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at IN4 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at IN3 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at IN2 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at IN1 exceeds its threshold. The open-drain output has a 30A internal pullup to VCC. Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output has a 30A internal pullup. Monitored Input Voltage 1. See Table 1 for the input voltage threshold. Monitored Input Voltage 2. See Table 1 for the input voltage threshold. Monitored Input Voltage 3. See Table 1 for the input voltage threshold. Monitored Input Voltage 4. See Table 1 for the input voltage threshold. Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance. Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
MAX16060/MAX16061/MAX16062
5
WDI
6 7 8 9 10 11 12
GND VCC OUT5 OUT6 OUT7 OUT8 MR
13
SRT MARGIN OUT4 OUT3 OUT2 OUT1 RESET IN1 IN2 IN3 IN4 TOL EP
14 15 16 17 18
19 20 21 22 23 24 --
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Table 1. Input-Voltage-Threshold Selector
PART MAX16060A MAX16060B MAX16060C MAX16060D MAX16060E MAX16061A MAX16061B MAX16061C MAX16061D MAX16061E MAX16062A MAX16062B MAX16062C MAX16062D MAX16062E IN1 3.3 3.3 ADJ 3.3 ADJ 3.3 3.3 3.3 ADJ ADJ 3.3 3.3 3.3 ADJ ADJ IN2 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ 2.5 ADJ 2.5 2.5 ADJ IN3 ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN4 1.8 1.8 1.8 ADJ ADJ 1.8 1.8 ADJ 1.8 ADJ 1.8 1.8 ADJ 1.8 ADJ IN5 -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN6 -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ ADJ IN7 -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ IN8 -- -- -- -- -- -- -- -- -- -- ADJ ADJ ADJ ADJ ADJ
Note: Other fixed thresholds may be available. Contact factory for availability.
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Functional Diagrams
WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
OUT1
IN2 OUT2
OUTPUT DRIVER IN3 OUT3
EN IN4 OUT4
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16060D
MARGIN
Figure 1. MAX16060D Functional Diagram
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Functional Diagrams (continued)
WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
OUT1 IN2
OUT2 IN3
OUT3 OUTPUT DRIVER IN4
OUT4
IN5
OUT5
IN6
EN
OUT6
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16061C
MARGIN
Figure 2. MAX16061C Functional Diagram
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Functional Diagrams (continued)
WDI MR SRT VCC VCC WATCHDOG TIMER CIRCUIT TIMING RESET CIRCUIT IN1 RESET
OUT1 IN2
OUT2 IN3
OUT3 OUTPUT DRIVER IN4
OUT4
IN5
OUT5
IN6 OUT6
IN7 OUT7
IN8
EN
OUT8
VCC TOL REFERENCE
VCC UNDERVOLTAGE LOCKOUT VCC MAX16062C
MARGIN
Figure 3. MAX16062C Functional Diagram
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Detailed Description
The MAX16060/MAX16061/MAX16062 are 1% accurate low-voltage, quad-/hex-/octal-voltage P supervisors in a small thin QFN package. These devices provide supervisory functions for complex multivoltage systems. The MAX16060 monitors four voltages; the MAX16061 monitors six voltages; and the MAX16062 monitors eight voltages. These supervisors offer independent outputs for each monitored voltage along with a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds or the manual reset input is asserted. The reset output remains asserted for the reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. The minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. All open-drain outputs have internal 30A pullups that eliminate the need for external pullup resistors. However, each output can be driven with an external voltage up to 5.5V. Other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. An additional feature is a watchdog timer that asserts RESET when the watchdog timeout period (1.6s typ) is exceeded. The watchdog timer can be disabled by leaving WDI unconnected.
Window Detection
A window detector circuit uses two inputs in the configuration shown in Figure 6. External resistors set the two threshold voltages of the window detector circuit. External logic gates create the OUT signal. The window detection width is the difference between the threshold voltages (Figure 7).
5V
VCC V1 V2 V3 V4 IN1 IN2 IN3 IN4 MAX16060 OUT1 OUT2 OUT3 OUT4 GND
Figure 4. Quad Undervoltage Detector with LED Indicators
5V D1
Applications Information
Undervoltage-Detection Circuit
The open-drain outputs of the MAX16060/ MAX16061/MAX16062 can be configured to detect an undervoltage condition. Figure 4 shows a configuration where an LED turns on when the comparator output is low, indicating an undervoltage condition. These devices can also be used in applications such as system supervisory monitoring, multivoltage level detection, and VCC bar-graph monitoring (Figure 5).
VIN (5V) VCC IN1 OUT2 IN2 MAX16060 OUT3 D4 D3 OUT1 D2
IN3
Tolerance (TOL)
The MAX16060/MAX16061/MAX16062 feature a pinselectable threshold tolerance. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to VCC to select 10% threshold tolerance.
IN4 GND OUT4
Figure 5. VCC Bar-Graph Monitoring
14
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
VTH1 =
(1 + R1) (VTH + VTH_HYS) R2
5V R1 IN1 R2 IN2 IN3 R3 IN4 R4 GND OUT4 VCC OUT1 MAX16060E OUT2 OUT3
VINTH
R1
R2 OUT
INPUT
VTH
V R1 = R2( INTH - 1 VTH
)
Figure 8. Setting the Adjustable Input
R3 (1 + R4) VTH
VTH4 =
Adjustable Input
These devices offer several monitor options with adjustable input thresholds (see Table 1). The threshold voltage at each adjustable IN_ input is typically 0.394V (TOL = GND) or 0.373V (TOL = VCC). To monitor a voltage VINTH, connect a resistive-divider network to the circuit as shown in Figure 8. VINTH = VTH ((R1/R2) + 1) R1 = R2 ((VINTH/VTH) - 1) Large resistors can be used to minimize current through the external resistors. For greater accuracy, use lowervalue resistors.
Figure 6. Window Detection
OUT1 V TH1
Unused Inputs
OUT4 V TH4
Connect any unused IN_ inputs to a voltage above its threshold.
OUT_ Outputs
The OUT_ outputs go low when their respective IN_ inputs drop below their specified thresholds. The output is open drain with a 30A internal pullup to VCC. For many applications, no external pullup resistor is required to interface with other logic devices. An external pullup resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 9).
OUT V TH
Figure 7. Output Response of Window Detector Circuit
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
VCC = 3.3V 5V
IN_ VTH_ VTH_
100k VCC VCC
RESET 90% 10% tRD tRP
OUT_
RESET
MAX16060 MAX16061 MAX16062 GND GND
OUT_
90% 10% tD tD
Figure 9. Interfacing to a Different Logic Supply Voltage
Figure 10. Output Timing Diagram
RESET Output
RESET asserts low when any of the monitored voltages fall below their respective thresholds or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and MR is deasserted (see Figure 10). This open-drain output has a 30A internal pullup. An external pullup resistor to any voltage from 0 to 5.5V overrides the internal pullup if interfacing to different logic supply voltages. Internal circuitry prevents reverse current flow from the external pullup voltage to VCC (Figure 9).
Manual Reset Input (MR)
Many P-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts RESET low. RESET remains asserted while MR is low, and during the reset timeout period (140ms min) after MR returns high. The MR input has an internal 20k pullup resistor to VCC, so it can be left unconnected if not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function. External debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environment, connecting a 0.1F capacitor from MR to GND provides additional noise immunity.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommodate a variety of P applications. Adjust the reset timeout period (t RP ) by connecting a capacitor (C SRT ) between SRT and GND. Calculate the reset timeout capacitor as follows: t (s) x ISRT CSRT (F) = RP VTH _ SRT Connect SRT to VCC for a factory-programmed reset timeout of 140ms (min).
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors
Margin Output Disable (MARGIN)
MARGIN allows system-level testing while power supplies are adjusted from their nominal voltages. Drive MARGIN low to force RESET and OUT_ high, regardless of the voltage at any monitored input. The state of each output does not change while MARGIN = GND. The watchdog timer continues to run when MARGIN is low, and if a timeout occurs, RESET will assert tMD after MARGIN is deasserted. The MARGIN input is internally pulled up to VCC. Leave MARGIN unconnected or connect to VCC if unused. 1.735V), RESET is asserted and all OUT_ are asserted low. This eliminates an incorrect RESET or OUT_ output state as VCC drops below the normal VCC operational voltage range of 1.98V to 5.5V. During power-up as V CC rises above 1V, RESET is asserted and all OUT_ are asserted low until V CC exceeds the UVLO threshold. As VCC exceeds the UVLO threshold, all inputs are monitored and the correct output state appears at all the outputs. This also ensures that RESET and all OUT_ are in the correct state once VCC reaches the normal VCC operational range.
MAX16060/MAX16061/MAX16062
Undervoltage Lockout (UVLO)
The MAX16060/MAX16061/MAX16062 feature a VCC undervoltage lockout (UVLO) that preserves a reset status even if VCC falls as low as 1V. The undervoltage lockout circuitry monitors the voltage at VCC. If VCC falls below the UVLO falling threshold (typically
Power-Supply Bypassing
In noisy applications, bypass VCC to ground with a 0.1F capacitor as close to the device as possible. The additional capacitor improves transient immunity. For fast-rising VCC transients, additional capacitance may be required.
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1% Accurate, Quad-/Hex-/Octal-Voltage P Supervisors MAX16060/MAX16061/MAX16062
Pin Configurations
MARGIN OUT1 OUT2 OUT1 OUT2 OUT3 SRT SRT 11 10 9 MR OUT6 OUT5 OUT4 VCC
TOP VIEW
TOP VIEW
12
11
10
9 RESET 16 IN1 17
15
14
13
12
RESET 13 IN1 14 IN2 15 TOL 16 +
8 7
MR OUT4
MARGIN
MAX16060
IN2 18 6 5 OUT3 IN3 19 VCC TOL 20 +
MAX16061
8 7 6
1 IN3
2 IN4
3 WDI
4 GND
1 IN4
2 IN5
3 IN6
4 WDI
5 GND
THIN QFN (4mm x 4mm)
SRT
THIN QFN (4mm x 4mm)
MARGIN 14 OUT1 OUT2 OUT3 16 OUT4 15
TOP VIEW
18 RESET 19 IN1 20 IN2 21 IN3 22 IN4 23 + TOL 24 1 IN5
17
13 12 11 10 MR OUT8 OUT7 OUT6 OUT5 VCC
MAX16062
9 8 7
2 IN6
3 IN7
4 IN8
5 WDI
6 GND
THIN QFN (4mm x 4mm)
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 16 TQFN 20 TQFN 24 TQFN PACKAGE CODE T1644-4 T2044-3 T2444-4 DOCUMENT NO. 21-0139 21-0139 21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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